As the demand for higher performance semiconductor devices, such as integrated circuits (ICs) increases, manufactures strive to improve the performance of the individual components of the integrated circuits. In particular, field affect transistors (FETs) represent major components of integrated circuits and increasing the switching speed of FETs in many cases leads directly to improved IC performance. One method of increasing transistor switching speed is to increase the carrier mobility of the FETs. This is particularly important with respect to PMOS metal-oxide-semiconductor (MOS) transistors that are typically used in complimentary-MOS (CMOS) devices. To increase the switching speed and current gain within P-type MOS (PMOS) transistors, techniques have been developed to apply stress to the channel regions of the PMOS transistors. Applying stress and strain to the channel region of PMOS transistors strings the crystal and lattice within the channel region. In the case of silicon substrate technology, the Si—Si bonds are stressed, such that charge carriers move through the lattice at much higher rates than in an unstrained lattice.
A well-known technique for applying stress to the channel region of PMOS devices is to embed a silicon-germanium (SiGe) region into the source and drain regions of the FET. The lattice constant of SiGe does not match the lattice constant of a crystalline silicon substrate. Accordingly, stress (or more commonly referred to as “strain”) is created at the interface between the SiGe and the silicon substrate. Where SiGe material is embedded on opposite sides of the channel, the strain propagates through the region of the silicon lattice forming the channel of the FET.
While embedding SiGe in the source and drain regions of a PMOS transistor improves the transistor performance, integration of an embedded SiGe material into a CMOS process flow is extremely challenging. A common technique for introducing SiGe involves the epitaxial deposition of SiGe in regions of the substrate adjacent the gate electrode of the FET. For example, U.S. Pat. Pub. No. 2007/132038 describes a technique for embedding epitaxially-grown SiGe in the source and drain regions of an FET. The technique involves forming recesses in the substrate and epitaxially depositing SiGe into the source and drain regions of the substrate. The epitaxial deposition process is carried out for a predetermined amount of time in order to form a SiGe layer to a predetermined thickness.
Various substrate etching and epitaxial deposition techniques have been developed to provide epitaxial source and drain regions. For example, U.S. Pat. No. 7,195,985 discloses an etching and deposition technique in which the substrate etching and the subsequent epitaxial deposition is performed in the same reactor.
Further development of deposition methods, such as selective deposition of SiGe layers is described in U.S. Pat. No. 7,166,528. A deposition technique is disclosed in which silane gas is used as a precursor for the selective deposition of silicon-containing compounds, such as SiGe. The process also includes the introduction of a dopant and an etchant during the SiGe epitaxial deposition process. The dopant provides the SiGe material with various conductive characteristics, and the etchant functions to remove SiGe from surface features of the substrate.
While the use of SiGe embedded regions in the source and drain regions of an FET provides an effective means for stressing the channel region of the FET and improving its performance, epitaxial deposition processes can be difficult to control. In particular, the thickness of the epitaxially-deposited SiGe is important to efficient device processing. The thickness of the SiGe needs to be carefully controlled in proximity to the gate electrode of a PMOS device in order to avoid interference with other process operations, such as ion implantation into the channel region. For example, halo regions and extension regions can be formed in the channel region using an angled ion implantation process. Excessive thickness of the epitaxially-deposited SiGe in proximity to the gate electrode can interfere with the angled ion implantation and alter the doping profile of implanted regions within the FET channel. Accordingly, improvements in process technology are necessary to provide improve control of the SiGe epitaxial deposition process used in the fabrication of semiconductor devices.